The present invention relates in general to the design of integrated circuits, and in particular to a method for pipeline depth exploration in a register transfer level design description of an electronic circuit, and a corresponding computer system for pipeline depth exploration in a register transfer level design description of an electronic circuit. Still more particularly, the present invention relates to a data processing program and a computer program product for pipeline depth exploration in a register transfer level design description of an electronic circuit.
A common case in today's server Hardware Description Language (HDL) design is that existing logic of an electronic circuit, e.g. a netlist or a VHDL source description, needs to be migrated to fit different cycle time requirements or to be adapted to a new technology. Further existing electronic circuit design with pipelined logic should be adapted to new technology. There is no automated way to explore the maximum frequency for optimal performance. Case studies have shown that even entire pipeline stage can be saved when logic is balanced across the different stages. Right now this could be done manually but it would be a very time-consuming task since slacks between registers are to be checked and moved or removed manually for slack balancing. Also chip performance is lost due to lack of pervasive cross-cycle optimization.